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[/] [test_project/] [trunk/] [bench/] [verilog/] [orpsoc_testbench.v] - Rev 41

Rev	Log message	Author	Age	Path
40	Change name of file and module of orpsoc_top module	julius	5836d 14h	/test_project/trunk/bench/verilog/orpsoc_testbench.v
34	Fixed up couple of things. Changed way the test name is defined in sim Makefile	julius	5837d 17h	/test_project/trunk/bench/verilog/orpsoc_testbench.v
32	Looks like basic icarus tests passing. Todo is a list of timeouts for the rtl sim	julius	5839d 09h	/test_project/trunk/bench/verilog/orpsoc_testbench.v
31	Further progress with orpsoc test setup	julius	5839d 10h	/test_project/trunk/bench/verilog/orpsoc_testbench.v
30	Updating bench	julius	5841d 15h	/test_project/trunk/bench/verilog/orpsoc_testbench.v
26	Adding testbench and makefile update	julius	5842d 19h	/test_project/trunk/bench/verilog/orpsoc_testbench.v