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[/] [test_project/] [trunk/] [bench/] [verilog/] [orpsoc_testbench.v] - Rev 51

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46 Flash memory now also disabled when SDRAM disabled, which is by default. Ethernet now enabled by defining USE_ETHERNET, otherwise it is disabled by default. Default icarus tests now very fast due to this julius 5824d 07h /test_project/trunk/bench/verilog/orpsoc_testbench.v
45 Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default julius 5825d 00h /test_project/trunk/bench/verilog/orpsoc_testbench.v
43 Added some verilator lint controls, made icarus script much more concise. First stage of verilation now works julius 5831d 07h /test_project/trunk/bench/verilog/orpsoc_testbench.v
40 Change name of file and module of orpsoc_top module julius 5832d 02h /test_project/trunk/bench/verilog/orpsoc_testbench.v
34 Fixed up couple of things. Changed way the test name is defined in sim Makefile julius 5833d 06h /test_project/trunk/bench/verilog/orpsoc_testbench.v
32 Looks like basic icarus tests passing. Todo is a list of timeouts for the rtl sim julius 5834d 22h /test_project/trunk/bench/verilog/orpsoc_testbench.v
31 Further progress with orpsoc test setup julius 5834d 22h /test_project/trunk/bench/verilog/orpsoc_testbench.v
30 Updating bench julius 5837d 03h /test_project/trunk/bench/verilog/orpsoc_testbench.v
26 Adding testbench and makefile update julius 5838d 07h /test_project/trunk/bench/verilog/orpsoc_testbench.v

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