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[/] [test_project/] [trunk/] [bench/] [verilog/] [orpsoc_testbench_defines.v] - Rev 42

Rev	Log message	Author	Age	Path
34	Fixed up couple of things. Changed way the test name is defined in sim Makefile	julius	5683d 20h	/test_project/trunk/bench/verilog/orpsoc_testbench_defines.v
30	Updating bench	julius	5687d 17h	/test_project/trunk/bench/verilog/orpsoc_testbench_defines.v
26	Adding testbench and makefile update	julius	5688d 21h	/test_project/trunk/bench/verilog/orpsoc_testbench_defines.v