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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_startup/] [OR1K_startup.v] - Rev 57

Rev	Log message	Author	Age	Path
45	Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default	julius	5679d 06h	/test_project/trunk/rtl/verilog/components/or1k_startup/OR1K_startup.v
19	the rest of the design	unneback	5693d 14h	/test_project/trunk/rtl/verilog/components/or1k_startup/OR1K_startup.v