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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_startup/] [OR1K_startup_generic.v] - Rev 48

Rev	Log message	Author	Age	Path
34	Fixed up couple of things. Changed way the test name is defined in sim Makefile	julius	6032d 08h	/test_project/trunk/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v
19	the rest of the design	unneback	6038d 10h	/test_project/trunk/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v