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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_startup/] [OR1K_startup_generic.v] - Rev 60

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34 Fixed up couple of things. Changed way the test name is defined in sim Makefile julius 5770d 04h /test_project/trunk/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v
19 the rest of the design unneback 5776d 06h /test_project/trunk/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v

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