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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_startup/] [spi_flash_clgen.v] - Rev 42

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42 Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it. julius 5665d 19h /test_project/trunk/rtl/verilog/components/or1k_startup/spi_flash_clgen.v
19 the rest of the design unneback 5673d 03h /test_project/trunk/rtl/verilog/components/or1k_startup/spi_clgen.v

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