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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_startup/] [spi_flash_top.v] - Rev 48

Rev	Log message	Author	Age	Path
42	Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it.	julius	6030d 15h	/test_project/trunk/rtl/verilog/components/or1k_startup/spi_flash_top.v
22	compiles with icarus. basic make script done	julius	6037d 02h	/test_project/trunk/rtl/verilog/components/or1k_startup/spi_top.v
19	the rest of the design	unneback	6038d 00h	/test_project/trunk/rtl/verilog/components/or1k_startup/spi_top.v