URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_top/] [or1k_top.v] - Rev 57

Rev	Log message	Author	Age	Path
42	Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it.	julius	5682d 20h	/test_project/trunk/rtl/verilog/components/or1k_top/or1k_top.v
18	the rest of the design	unneback	5690d 04h	/test_project/trunk/rtl/verilog/components/or1k_top/or1k_top.v