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Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [ram_wb/] [ram_wb.v] - Rev 45

Rev	Log message	Author	Age	Path
45	Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default	julius	5658d 21h	/test_project/trunk/rtl/verilog/components/ram_wb/ram_wb.v