URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [wb_sdram_ctrl/] [wb_sdram_ctrl.v] - Rev 52

Rev	Log message	Author	Age	Path
43	Added some verilator lint controls, made icarus script much more concise. First stage of verilation now works	julius	5889d 11h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl.v
42	Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it.	julius	5890d 03h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl.v
38	Actually that last fix caused another bug. This, and the original, are now fixed. Dhrystone ICDC passes	julius	5890d 10h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
37	Hacked a bug fix - probably due to DCache bugs which are due to be fixed - dhrystone-icdc test still does not complete	julius	5891d 06h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
22	compiles with icarus. basic make script done	julius	5896d 13h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
18	the rest of the design	unneback	5897d 12h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v