URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [wb_sdram_ctrl/] [wb_sdram_ctrl.v] - Rev 60

Rev	Log message	Author	Age	Path
43	Added some verilator lint controls, made icarus script much more concise. First stage of verilation now works	julius	5685d 09h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl.v
42	Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it.	julius	5686d 01h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl.v
38	Actually that last fix caused another bug. This, and the original, are now fixed. Dhrystone ICDC passes	julius	5686d 07h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
37	Hacked a bug fix - probably due to DCache bugs which are due to be fixed - dhrystone-icdc test still does not complete	julius	5687d 04h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
22	compiles with icarus. basic make script done	julius	5692d 11h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
18	the rest of the design	unneback	5693d 10h	/test_project/trunk/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v