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[/] [test_project/] [trunk/] [rtl/] [verilog/] [orpsoc_top.v] - Rev 45

Rev	Log message	Author	Age	Path
45	Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default	julius	5871d 21h	/test_project/trunk/rtl/verilog/orpsoc_top.v
42	Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it.	julius	5878d 20h	/test_project/trunk/rtl/verilog/orpsoc_top.v
40	Change name of file and module of orpsoc_top module	julius	5879d 00h	/test_project/trunk/rtl/verilog/orpsoc_top.v