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[/] [test_project/] [trunk/] [sim/] [bin/] [Makefile] - Rev 59

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Rev Log message Author Age Path
58 Further documentation in the main makefile julius 5674d 20h /test_project/trunk/sim/bin/Makefile
57 A better explanation at top of main sim makefile julius 5675d 17h /test_project/trunk/sim/bin/Makefile
56 OR1k sim tests now implemented and working julius 5675d 18h /test_project/trunk/sim/bin/Makefile
55 Systemc vcd file name based on test name which is passed via command line when the executable is run julius 5675d 19h /test_project/trunk/sim/bin/Makefile
54 Added verilog UART decoder for event-driven sim tests (icarus, nc) - removed MAC tests from multiplier tests - not returning right results for some reason - should be looked at julius 5675d 21h /test_project/trunk/sim/bin/Makefile
53 verilator test loop in makefile - same results as icarus julius 5676d 10h /test_project/trunk/sim/bin/Makefile
52 Enabled own printf function using UART as output julius 5676d 11h /test_project/trunk/sim/bin/Makefile
50 Tracing enabled on Verilator model julius 5679d 14h /test_project/trunk/sim/bin/Makefile
49 Verilator model now builds OK. julius 5679d 23h /test_project/trunk/sim/bin/Makefile
48 Closer to working verilator build julius 5680d 15h /test_project/trunk/sim/bin/Makefile
47 Basic verilator model getting closer. Included more modules from the example by Jeremy Bennett. Final cplusplus executable from verilator output fails to link properly julius 5680d 19h /test_project/trunk/sim/bin/Makefile
45 Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default julius 5682d 16h /test_project/trunk/sim/bin/Makefile
44 Beginnings of verilator build - much still to do but the design can now at least be verilated julius 5688d 19h /test_project/trunk/sim/bin/Makefile
43 Added some verilator lint controls, made icarus script much more concise. First stage of verilation now works julius 5688d 23h /test_project/trunk/sim/bin/Makefile
42 Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it. julius 5689d 15h /test_project/trunk/sim/bin/Makefile
41 Removed duplicate or1200_defines.v and timescale.v files julius 5689d 17h /test_project/trunk/sim/bin/Makefile
39 Removed auto logging of processor state, added option to enable it in makefile, documented way the tests are done in makefile and that should probably be moved to some readme at some point julius 5689d 19h /test_project/trunk/sim/bin/Makefile
36 Couple of makefile updates julius 5690d 21h /test_project/trunk/sim/bin/Makefile
35 Fixed or1200_defines confusion julius 5690d 21h /test_project/trunk/sim/bin/Makefile
34 Fixed up couple of things. Changed way the test name is defined in sim Makefile julius 5690d 22h /test_project/trunk/sim/bin/Makefile

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