OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [sw/] [except/] [Makefile] - Rev 52

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
52 Enabled own printf function using UART as output julius 5618d 18h /test_project/trunk/sw/except/Makefile
45 Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default julius 5624d 23h /test_project/trunk/sw/except/Makefile
25 Adding sw dir PROPERLY julius 5638d 08h /test_project/trunk/sw/except/Makefile

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.