OpenCores
URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [src/] [core.vhd] - Rev 32

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
32 Finished up changes needed to make memory reading actually work.
Push and Pop now work		 earlz 4573d 18h /tinycpu/trunk/src/core.vhd
31 Removed the infamous TRData latch from ALU. Now synthesizes (sorta) warning free. No latches are used. earlz 4574d 14h /tinycpu/trunk/src/core.vhd
30 After a long weekend of thinking how to do this.. I've decided instead to not strive for a single-cycle computer.
Now, instead, ALU operations will be 2 cycle along with memory operations, and data movement operations are still 1 cycle		 earlz 4574d 14h /tinycpu/trunk/src/core.vhd
29 Well, added a testcase for testing the ALU bitwise operations and found a very large problem.
I'm pretty sure that the decoder needs to be partially unclocked because it essentially makes the ALU clocked how it is now, which is very bad.		 earlz 4577d 21h /tinycpu/trunk/src/core.vhd
28 Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
Now it's truly single-cycle and without all the weird regIn stuff on the carryovers		 earlz 4578d 15h /tinycpu/trunk/src/core.vhd
27 Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile.
As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later		 earlz 4578d 21h /tinycpu/trunk/src/core.vhd
25 Wait for memory state now works as expected, and opcode `mov [reg], immd` works now earlz 4579d 03h /tinycpu/trunk/src/core.vhd
24 Good news, mov to IP actually works as expected! earlz 4579d 20h /tinycpu/trunk/src/core.vhd
23 Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core		 earlz 4579d 21h /tinycpu/trunk/src/core.vhd
21 The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. earlz 4580d 13h /tinycpu/trunk/src/core.vhd
20 fuck it. All sorts of broken, will try to fix it tomorrow earlz 4581d 12h /tinycpu/trunk/src/core.vhd
19 Got beginning of core/decoder for the CPU earlz 4581d 14h /tinycpu/trunk/src/core.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.