URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [src/] [registerfile.vhd] - Rev 39

Rev	Log message	Author	Age	Path
28	Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted. Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle. Now it's truly single-cycle and without all the weird regIn stuff on the carryovers	earlz	4574d 22h	/tinycpu/trunk/src/registerfile.vhd
27	Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile. As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later	earlz	4575d 04h	/tinycpu/trunk/src/registerfile.vhd
19	Got beginning of core/decoder for the CPU	earlz	4577d 20h	/tinycpu/trunk/src/registerfile.vhd
12	registerfile has ports for every register now makefile now uses GHW file format for gtkwave instead of VCD	earlz	4587d 07h	/tinycpu/trunk/src/registerfile.vhd
6	Reworked memory code to hopefully synthesize better	earlz	4592d 10h	/tinycpu/trunk/src/registerfile.vhd
5	Modified registerfile to be dual-port for both read and write	earlz	4592d 21h	/tinycpu/trunk/src/registerfile.vhd
3	Updated registerfile to have 2 read ports Added super rough design document mainly just for brainstorming	earlz	4593d 21h	/tinycpu/trunk/src/registerfile.vhd
2	Initial commit	earlz	4593d 22h	/tinycpu/trunk/src/registerfile.vhd