URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [testbench/] [blockram_tb.vhd] - Rev 36

Rev	Log message	Author	Age	Path
11	Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge	earlz	4591d 04h	/tinycpu/trunk/testbench/blockram_tb.vhd
10	Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs	earlz	4591d 05h	/tinycpu/trunk/testbench/blockram_tb.vhd
9	Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench	earlz	4591d 12h	/tinycpu/trunk/testbench/blockram_tb.vhd
8	Added blockram for inferring actual block RAM. Now we need a memory controller, not a crappy memory emulation thing	earlz	4592d 12h	/tinycpu/trunk/testbench/blockram_tb.vhd