URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

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[/] [tinycpu/] [trunk/] [testbench/] [top_tb.vhd] - Rev 37

Rev	Log message	Author	Age	Path
37	Worked on the assembler more Added a memory mapped port to memory.vhd. This change causes a lot of latches to be inferred in synthesis however, so this will have to change some	earlz	4552d 07h	/tinycpu/trunk/testbench/top_tb.vhd
28	Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted. Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle. Now it's truly single-cycle and without all the weird regIn stuff on the carryovers	earlz	4558d 09h	/tinycpu/trunk/testbench/top_tb.vhd
25	Wait for memory state now works as expected, and opcode `mov [reg], immd` works now	earlz	4558d 21h	/tinycpu/trunk/testbench/top_tb.vhd
23	Added top module for testing how our memory and cpu will work together. (hint: success) Messing around with a small timing issue in core	earlz	4559d 15h	/tinycpu/trunk/testbench/top_tb.vhd