OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [scripts/] [reglib.py] - Rev 110

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
110 Updated rgen script, added documentation for rgen ghutchis 4988d 09h /tv80/trunk/scripts/reglib.py
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.
ghutchis 5462d 07h /tv80/trunk/scripts/reglib.py
84 New directory structure. root 5722d 20h /tv80/trunk/scripts/reglib.py
67 Updated register generator based on testing with simple_gmii. Changed
how interrupt output mux is created, fixed many bugs.
ghutchis 7191d 08h /tv80/trunk/scripts/reglib.py
64 Created rgen script and expanded available register types ghutchis 7192d 07h /tv80/trunk/scripts/reglib.py
59 Added lib for generating MPU interfaces ghutchis 7226d 12h /tv80/trunk/scripts/reglib.py

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.