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[/] [uart16550/] [tags/] [asyst_3/] [rtl/] [verilog/] [uart_regs.v] - Rev 106

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Rev	Log message	Author	Age	Path
106	New directory structure.	root	5629d 23h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
77	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		8205d 16h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
68	lsr[7] was not showing overrun errors.	mohor	8259d 20h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
66	rx push changed to be only one cycle wide.	mohor	8266d 20h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
64	Warnings cleared.	mohor	8268d 01h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
63	Synplicity was having troubles with the comment.	mohor	8268d 01h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8269d 23h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
59	MSR register fixed.	mohor	8272d 20h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
58	After reset modem status register MSR should be reset.	mohor	8272d 23h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
56	thre irq should be cleared only when being source of interrupt.	mohor	8273d 23h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8275d 00h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
52	Scratch register added	gorban	8276d 13h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8280d 18h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8283d 11h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8288d 13h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8290d 11h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
44	fixed more typo bugs	gorban	8304d 11h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
43	lsr1r error fixed.	mohor	8304d 18h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
42	ti_int_pnd error fixed.	mohor	8304d 18h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v
41	ti_int_d error fixed.	mohor	8304d 18h	/uart16550/tags/asyst_3/rtl/verilog/uart_regs.v

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[/] [uart16550/] [tags/] [asyst_3/] [rtl/] [verilog/] [uart_regs.v] - Rev 106

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