URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [bench/] [verilog/] [uart_device.v] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5883d 04h	/uart16550/trunk/bench/verilog/uart_device.v
93	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7692d 10h	/uart16550/trunk/bench/verilog/uart_device.v