URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [timescale.v] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5866d 07h	/uart16550/trunk/rtl/verilog/timescale.v
29	Things connected to parity changed. Clock devider changed.	mohor	8620d 20h	/uart16550/trunk/rtl/verilog/timescale.v
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8622d 01h	/uart16550/trunk/rtl/verilog/timescale.v