URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [uart_tx.v] - Rev 10

Rev	Log message	Author	Age	Path
9	Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate.	motilito	4778d 17h	/uart2bus/trunk/verilog/rtl/uart_tx.v
2	Uploaded the initial project version.	motilito	5423d 15h	/uart2bus/trunk/verilog/rtl/uart_tx.v