OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [iseProject.gise] - Rev 39

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
39 Working on testbench leonardoaraujo.santos 5256d 23h /uart_block/trunk/hdl/iseProject/iseProject.gise
38 Adding testbench validation ....
We could still have some problem on the data_ready of serial_receiver block		 leonardoaraujo.santos 5259d 19h /uart_block/trunk/hdl/iseProject/iseProject.gise
37 Working on the documentation leonardoaraujo.santos 5260d 20h /uart_block/trunk/hdl/iseProject/iseProject.gise
36 Working on the documentation leonardoaraujo.santos 5260d 20h /uart_block/trunk/hdl/iseProject/iseProject.gise
35 Bug really fixed... Some testbench results saved... Now would be a nice Idea to start thinking about documentation... leonardoaraujo.santos 5263d 21h /uart_block/trunk/hdl/iseProject/iseProject.gise
34 Seems that the issue is solved (working on Spartan3E board and confirmed with chipscope) leonardoaraujo.santos 5264d 00h /uart_block/trunk/hdl/iseProject/iseProject.gise
31 Working on documentation and on Chipscope leonardoaraujo.santos 5265d 17h /uart_block/trunk/hdl/iseProject/iseProject.gise
30 Preparing to work with chipscope leonardoaraujo.santos 5265d 17h /uart_block/trunk/hdl/iseProject/iseProject.gise
29 Preparing to work with chipscope leonardoaraujo.santos 5265d 18h /uart_block/trunk/hdl/iseProject/iseProject.gise
28 Changing wrong datasheet of Spartan3A kit for newer one.... Detected some bug on the reception (When is fast it seems that the reception could be wrong...) leonardoaraujo.santos 5265d 19h /uart_block/trunk/hdl/iseProject/iseProject.gise
27 First version seems working nice on the PC!!! leonardoaraujo.santos 5265d 19h /uart_block/trunk/hdl/iseProject/iseProject.gise
20 Finishing at least the tests on testbench.... Was good to verify that the uart_control should be redesigned to allow concurrent receive and to clean the code... leonardoaraujo.santos 5267d 19h /uart_block/trunk/hdl/iseProject/iseProject.gise
19 Working on the top wishbone slave testbench.... still need some fixes (Both on the testbench and on the uart_control.vhd) leonardoaraujo.santos 5267d 20h /uart_block/trunk/hdl/iseProject/iseProject.gise
18 sdsd leonardoaraujo.santos 5268d 02h /uart_block/trunk/hdl/iseProject/iseProject.gise
17 Working on slave testbench and fixing some bugs leonardoaraujo.santos 5268d 04h /uart_block/trunk/hdl/iseProject/iseProject.gise
16 Adding testbench for wishbone slave module leonardoaraujo.santos 5268d 04h /uart_block/trunk/hdl/iseProject/iseProject.gise
15 Taking out some warnings and transparent latches from the design leonardoaraujo.santos 5268d 05h /uart_block/trunk/hdl/iseProject/iseProject.gise
14 Fixing some warnings... Adding wishbone slave leonardoaraujo.santos 5269d 01h /uart_block/trunk/hdl/iseProject/iseProject.gise
13 Working on uart_control testbench... also applying some fixes... leonardoaraujo.santos 5269d 02h /uart_block/trunk/hdl/iseProject/iseProject.gise
12 Working on the communication blocks leonardoaraujo.santos 5269d 03h /uart_block/trunk/hdl/iseProject/iseProject.gise

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.