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Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [isim.log] - Rev 39

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Rev	Log message	Author	Age	Path
39	Working on testbench	leonardoaraujo.santos	4662d 23h	/uart_block/trunk/hdl/iseProject/isim.log
38	Adding testbench validation .... We could still have some problem on the data_ready of serial_receiver block	leonardoaraujo.santos	4665d 19h	/uart_block/trunk/hdl/iseProject/isim.log
35	Bug really fixed... Some testbench results saved... Now would be a nice Idea to start thinking about documentation...	leonardoaraujo.santos	4669d 22h	/uart_block/trunk/hdl/iseProject/isim.log
32	Change baud generator to create a overclock frequency of 8x the baud rate.... Change the serial receiver to sample the signal on the middle of the serial input, now it's using only the overclocked baud...	leonardoaraujo.santos	4671d 05h	/uart_block/trunk/hdl/iseProject/isim.log
24	Working on testbench and refactoring... now we could start some tests on the board...	leonardoaraujo.santos	4673d 01h	/uart_block/trunk/hdl/iseProject/isim.log
23	Working on uart_control refactoring	leonardoaraujo.santos	4673d 02h	/uart_block/trunk/hdl/iseProject/isim.log
22	Refactoring the uart_control	leonardoaraujo.santos	4673d 05h	/uart_block/trunk/hdl/iseProject/isim.log
21	Preparing to rewrite uart_control, adding pin to indicate data available at the RX	leonardoaraujo.santos	4673d 11h	/uart_block/trunk/hdl/iseProject/isim.log
20	Finishing at least the tests on testbench.... Was good to verify that the uart_control should be redesigned to allow concurrent receive and to clean the code...	leonardoaraujo.santos	4673d 19h	/uart_block/trunk/hdl/iseProject/isim.log
19	Working on the top wishbone slave testbench.... still need some fixes (Both on the testbench and on the uart_control.vhd)	leonardoaraujo.santos	4673d 20h	/uart_block/trunk/hdl/iseProject/isim.log
18	sdsd	leonardoaraujo.santos	4674d 03h	/uart_block/trunk/hdl/iseProject/isim.log
17	Working on slave testbench and fixing some bugs	leonardoaraujo.santos	4674d 04h	/uart_block/trunk/hdl/iseProject/isim.log
16	Adding testbench for wishbone slave module	leonardoaraujo.santos	4674d 04h	/uart_block/trunk/hdl/iseProject/isim.log
15	Taking out some warnings and transparent latches from the design	leonardoaraujo.santos	4674d 05h	/uart_block/trunk/hdl/iseProject/isim.log
14	Fixing some warnings... Adding wishbone slave	leonardoaraujo.santos	4675d 01h	/uart_block/trunk/hdl/iseProject/isim.log
13	Working on uart_control testbench... also applying some fixes...	leonardoaraujo.santos	4675d 02h	/uart_block/trunk/hdl/iseProject/isim.log
12	Working on the communication blocks	leonardoaraujo.santos	4675d 03h	/uart_block/trunk/hdl/iseProject/isim.log
11	Adding uart_communication_block	leonardoaraujo.santos	4675d 05h	/uart_block/trunk/hdl/iseProject/isim.log
10	Working on the control unit part	leonardoaraujo.santos	4675d 09h	/uart_block/trunk/hdl/iseProject/isim.log
9	Adding Control unit for uart block	leonardoaraujo.santos	4675d 21h	/uart_block/trunk/hdl/iseProject/isim.log

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Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [isim.log] - Rev 39

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