URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_wishbone_slave.vhd] - Rev 29

Rev	Log message	Author	Age	Path
24	Working on testbench and refactoring... now we could start some tests on the board...	leonardoaraujo.santos	4589d 21h	/uart_block/trunk/hdl/iseProject/testUart_wishbone_slave.vhd
23	Working on uart_control refactoring	leonardoaraujo.santos	4589d 22h	/uart_block/trunk/hdl/iseProject/testUart_wishbone_slave.vhd
21	Preparing to rewrite uart_control, adding pin to indicate data available at the RX	leonardoaraujo.santos	4590d 07h	/uart_block/trunk/hdl/iseProject/testUart_wishbone_slave.vhd
20	Finishing at least the tests on testbench.... Was good to verify that the uart_control should be redesigned to allow concurrent receive and to clean the code...	leonardoaraujo.santos	4590d 15h	/uart_block/trunk/hdl/iseProject/testUart_wishbone_slave.vhd
19	Working on the top wishbone slave testbench.... still need some fixes (Both on the testbench and on the uart_control.vhd)	leonardoaraujo.santos	4590d 16h	/uart_block/trunk/hdl/iseProject/testUart_wishbone_slave.vhd
18	sdsd	leonardoaraujo.santos	4590d 23h	/uart_block/trunk/hdl/iseProject/testUart_wishbone_slave.vhd
17	Working on slave testbench and fixing some bugs	leonardoaraujo.santos	4591d 00h	/uart_block/trunk/hdl/iseProject/testUart_wishbone_slave.vhd
16	Adding testbench for wishbone slave module	leonardoaraujo.santos	4591d 00h	/uart_block/trunk/hdl/iseProject/testUart_wishbone_slave.vhd