URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [xilinxsim.ini] - Rev 19

Rev	Log message	Author	Age	Path
19	Working on the top wishbone slave testbench.... still need some fixes (Both on the testbench and on the uart_control.vhd)	leonardoaraujo.santos	4721d 09h	/uart_block/trunk/hdl/iseProject/xilinxsim.ini
10	Working on the control unit part	leonardoaraujo.santos	4722d 22h	/uart_block/trunk/hdl/iseProject/xilinxsim.ini
8	Solving some bugs in baud_generator.vhd	leonardoaraujo.santos	4723d 21h	/uart_block/trunk/hdl/iseProject/xilinxsim.ini
6	Adding baud generator	leonardoaraujo.santos	4724d 17h	/uart_block/trunk/hdl/iseProject/xilinxsim.ini
2	Starting here ....	leonardoaraujo.santos	4731d 21h	/uart_block/trunk/hdl/iseProject/xilinxsim.ini