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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [xst/] [work/] [hdllib.ref] - Rev 25

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24 Working on testbench and refactoring... now we could start some tests on the board... leonardoaraujo.santos 4574d 21h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
22 Refactoring the uart_control leonardoaraujo.santos 4575d 01h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
21 Preparing to rewrite uart_control, adding pin to indicate data available at the RX leonardoaraujo.santos 4575d 07h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
20 Finishing at least the tests on testbench.... Was good to verify that the uart_control should be redesigned to allow concurrent receive and to clean the code... leonardoaraujo.santos 4575d 15h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
19 Working on the top wishbone slave testbench.... still need some fixes (Both on the testbench and on the uart_control.vhd) leonardoaraujo.santos 4575d 16h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
16 Adding testbench for wishbone slave module leonardoaraujo.santos 4576d 00h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
15 Taking out some warnings and transparent latches from the design leonardoaraujo.santos 4576d 01h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
14 Fixing some warnings... Adding wishbone slave leonardoaraujo.santos 4576d 21h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
13 Working on uart_control testbench... also applying some fixes... leonardoaraujo.santos 4576d 22h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
11 Adding uart_communication_block leonardoaraujo.santos 4577d 01h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
6 Adding baud generator leonardoaraujo.santos 4579d 00h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
4 Working on receiver leonardoaraujo.santos 4586d 02h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
2 Starting here .... leonardoaraujo.santos 4586d 04h /uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref

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