URL https://opencores.org/ocsvn/usb_phy/usb_phy/trunk

Subversion Repositories usb_phy

[/] [usb_phy/] [trunk/] [rtl/] [verilog/] [usb_tx_phy.v] - Rev 12

Rev	Log message	Author	Age	Path
12	New directory structure.	root	5633d 12h	/usb_phy/trunk/rtl/verilog/usb_tx_phy.v
11	Fixed DPLL alignment in the rx_phy and bit stuffing errors in the tx_phy (if last bit bit was a stuff bit in a packet it was omitted).	rudi	7236d 13h	/usb_phy/trunk/rtl/verilog/usb_tx_phy.v
9	usb_rst is no longer or'ed with the incomming reset internally. Now usb_rst is simply an output, the application can decide how to utilize it.	rudi	7600d 17h	/usb_phy/trunk/rtl/verilog/usb_tx_phy.v
7	- Made core more robust against line noise - Added Error Checking and Reporting (See README.txt for more info)	rudi	7602d 05h	/usb_phy/trunk/rtl/verilog/usb_tx_phy.v
2	Created Directory Structure	rudi	8000d 08h	/usb_phy/trunk/rtl/verilog/usb_tx_phy.v