URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [busInterface/] [wishBoneBI.v] - Rev 42

Rev	Log message	Author	Age	Path
40	New directory structure.	root	5685d 10h	/usbhostslave/trunk/RTL/busInterface/wishBoneBI.v
37	usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project	sfielding	5882d 19h	/usbhostslave/trunk/RTL/busInterface/wishBoneBI.v
22	Release 1.2	sfielding	6563d 16h	/usbhostslave/trunk/RTL/busInterface/wishBoneBI.v
9	Fixed bus turn-around problems, added version number	sfielding	7195d 06h	/usbhostslave/trunk/RTL/busInterface/wishBoneBI.v
5	Removed html documentation	sfielding	7228d 05h	/usbhostslave/trunk/RTL/busInterface/wishBoneBI.v
2	Created	sfielding	7296d 16h	/usbhostslave/trunk/RTL/busInterface/wishBoneBI.v