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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [USBHostControlBI.v] - Rev 40

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Rev Log message Author Age Path
40 New directory structure. root 5900d 00h /usbhostslave/trunk/RTL/hostController/USBHostControlBI.v
37 usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project sfielding 6097d 10h /usbhostslave/trunk/RTL/hostController/USBHostControlBI.v
22 Release 1.2 sfielding 6778d 06h /usbhostslave/trunk/RTL/hostController/USBHostControlBI.v
18 Added dual clock, fixed slave bug, added reset register sfielding 7113d 19h /usbhostslave/trunk/RTL/hostController/USBHostControlBI.v
16 Added bus access to SOF timer sfielding 7252d 22h /usbhostslave/trunk/RTL/hostController/USBHostControlBI.v
14 Added LS keep alive, fixed clock recovery bug sfielding 7362d 06h /usbhostslave/trunk/RTL/hostController/USBHostControlBI.v
12 try again sfielding 7392d 21h /usbhostslave/trunk/RTL/hostController/USBHostControlBI.v
9 Fixed bus turn-around problems, added version number sfielding 7409d 20h /usbhostslave/trunk/RTL/hostController/USBHostControlBI.v
5 Removed html documentation sfielding 7442d 20h /usbhostslave/trunk/RTL/hostController/USBHostControlBI.v
2 Created sfielding 7511d 06h /usbhostslave/trunk/RTL/hostController/USBHostControlBI.v

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