URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacket.v] - Rev 44

Rev	Log message	Author	Age	Path
40	New directory structure.	root	5742d 05h	/usbhostslave/trunk/RTL/hostController/sendpacket.v
37	usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project	sfielding	5939d 14h	/usbhostslave/trunk/RTL/hostController/sendpacket.v
34	* empty log message *	sfielding	6618d 08h	/usbhostslave/trunk/RTL/hostController/sendpacket.v
22	Release 1.2	sfielding	6620d 11h	/usbhostslave/trunk/RTL/hostController/sendpacket.v
14	Added LS keep alive, fixed clock recovery bug	sfielding	7204d 10h	/usbhostslave/trunk/RTL/hostController/sendpacket.v
9	Fixed bus turn-around problems, added version number	sfielding	7252d 01h	/usbhostslave/trunk/RTL/hostController/sendpacket.v
7	Fixed some blocking assignments, changed module name, fixed SOF_TX_TIME	sfielding	7272d 00h	/usbhostslave/trunk/RTL/hostController/sendpacket.v
5	Removed html documentation	sfielding	7285d 00h	/usbhostslave/trunk/RTL/hostController/sendpacket.v
2	Created	sfielding	7353d 11h	/usbhostslave/trunk/RTL/hostController/sendpacket.v