URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [include/] [usbHostSlave_h.v] - Rev 40

Rev	Log message	Author	Age	Path
40	New directory structure.	root	5580d 20h	/usbhostslave/trunk/RTL/include/usbHostSlave_h.v
37	usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project	sfielding	5778d 05h	/usbhostslave/trunk/RTL/include/usbHostSlave_h.v
36	Revision 1.3 - Fixed input metastability and delay hazard issue	sfielding	5933d 17h	/usbhostslave/trunk/RTL/include/usbHostSlave_h.v
22	Release 1.2	sfielding	6459d 02h	/usbhostslave/trunk/RTL/include/usbHostSlave_h.v
20	Fixed RX clock recovery bug, and RX time out bug	sfielding	6690d 00h	/usbhostslave/trunk/RTL/include/usbHostSlave_h.v
18	Added dual clock, fixed slave bug, added reset register	sfielding	6794d 15h	/usbhostslave/trunk/RTL/include/usbHostSlave_h.v
16	Added bus access to SOF timer	sfielding	6933d 17h	/usbhostslave/trunk/RTL/include/usbHostSlave_h.v
14	Added LS keep alive, fixed clock recovery bug	sfielding	7043d 01h	/usbhostslave/trunk/RTL/include/usbHostSlave_h.v
12	try again	sfielding	7073d 17h	/usbhostslave/trunk/RTL/include/usbHostSlave_h.v
10	Added version number	sfielding	7090d 01h	/usbhostslave/trunk/RTL/include/usbHostSlave_h.v