URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [include/] [usbSlaveControl_h.v] - Rev 40

Rev	Log message	Author	Age	Path
40	New directory structure.	root	5580d 20h	/usbhostslave/trunk/RTL/include/usbSlaveControl_h.v
37	usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project	sfielding	5778d 06h	/usbhostslave/trunk/RTL/include/usbSlaveControl_h.v
22	Release 1.2	sfielding	6459d 02h	/usbhostslave/trunk/RTL/include/usbSlaveControl_h.v
14	Added LS keep alive, fixed clock recovery bug	sfielding	7043d 02h	/usbhostslave/trunk/RTL/include/usbSlaveControl_h.v
9	Fixed bus turn-around problems, added version number	sfielding	7090d 17h	/usbhostslave/trunk/RTL/include/usbSlaveControl_h.v
7	Fixed some blocking assignments, changed module name, fixed SOF_TX_TIME	sfielding	7110d 16h	/usbhostslave/trunk/RTL/include/usbSlaveControl_h.v
5	Removed html documentation	sfielding	7123d 16h	/usbhostslave/trunk/RTL/include/usbSlaveControl_h.v
2	Created	sfielding	7192d 02h	/usbhostslave/trunk/RTL/include/usbSlaveControl_h.v