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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [SIETransmitter.asf] - Rev 44

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Rev Log message Author Age Path
40 New directory structure. root 5900d 10h /usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf
37 usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project sfielding 6097d 20h /usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf
34 *** empty log message *** sfielding 6776d 14h /usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf
33 *** empty log message *** sfielding 6776d 17h /usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf
22 Release 1.2 sfielding 6778d 16h /usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf
14 Added LS keep alive, fixed clock recovery bug sfielding 7362d 16h /usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf
9 Fixed bus turn-around problems, added version number sfielding 7410d 06h /usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf
7 Fixed some blocking assignments, changed module name, fixed SOF_TX_TIME sfielding 7430d 06h /usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf
5 Removed html documentation sfielding 7443d 06h /usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf
2 Created sfielding 7511d 16h /usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf

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