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URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [processRxBit.v] - Rev 40

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Rev	Log message	Author	Age	Path
40	New directory structure.	root	5583d 12h	/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
37	usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project	sfielding	5780d 22h	/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
34	* empty log message *	sfielding	6459d 16h	/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
22	Release 1.2	sfielding	6461d 18h	/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
14	Added LS keep alive, fixed clock recovery bug	sfielding	7045d 18h	/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
12	try again	sfielding	7076d 09h	/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
9	Fixed bus turn-around problems, added version number	sfielding	7093d 08h	/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
7	Fixed some blocking assignments, changed module name, fixed SOF_TX_TIME	sfielding	7113d 08h	/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
5	Removed html documentation	sfielding	7126d 08h	/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
2	Created	sfielding	7194d 18h	/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v

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