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Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [processTxByte.v] - Rev 44

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43 Fixed bugs related to accessing low speed device via hub sfielding 5140d 00h /usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v
40 New directory structure. root 5717d 14h /usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v
37 usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project sfielding 5915d 00h /usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v
34 *** empty log message *** sfielding 6593d 18h /usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v
22 Release 1.2 sfielding 6595d 20h /usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v
14 Added LS keep alive, fixed clock recovery bug sfielding 7179d 20h /usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v
12 try again sfielding 7210d 11h /usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v
9 Fixed bus turn-around problems, added version number sfielding 7227d 11h /usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v
7 Fixed some blocking assignments, changed module name, fixed SOF_TX_TIME sfielding 7247d 10h /usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v
5 Removed html documentation sfielding 7260d 10h /usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v
2 Created sfielding 7328d 20h /usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v

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