URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [USBSlaveControlBI.v] - Rev 42

Rev	Log message	Author	Age	Path
40	New directory structure.	root	5717d 20h	/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v
37	usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project	sfielding	5915d 05h	/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v
22	Release 1.2	sfielding	6596d 02h	/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v
18	Added dual clock, fixed slave bug, added reset register	sfielding	6931d 15h	/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v
14	Added LS keep alive, fixed clock recovery bug	sfielding	7180d 01h	/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v
12	try again	sfielding	7210d 17h	/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v
9	Fixed bus turn-around problems, added version number	sfielding	7227d 16h	/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v
5	Removed html documentation	sfielding	7260d 15h	/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v
2	Created	sfielding	7329d 02h	/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v