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URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [slaveGetpacket.v] - Rev 44

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Rev Log message Author Age Path
40 New directory structure. root 5742d 06h /usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v
37 usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project sfielding 5939d 15h /usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v
34 *** empty log message *** sfielding 6618d 10h /usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v
22 Release 1.2 sfielding 6620d 12h /usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v
20 Fixed RX clock recovery bug, and RX time out bug sfielding 6851d 10h /usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v
18 Added dual clock, fixed slave bug, added reset register sfielding 6956d 01h /usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v
9 Fixed bus turn-around problems, added version number sfielding 7252d 02h /usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v
7 Fixed some blocking assignments, changed module name, fixed SOF_TX_TIME sfielding 7272d 01h /usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v
5 Removed html documentation sfielding 7285d 01h /usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v
2 Created sfielding 7353d 12h /usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v

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