URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] [usbSlaveControl.v] - Rev 40

Rev	Log message	Author	Age	Path
40	New directory structure.	root	5583d 04h	/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v
37	usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project	sfielding	5780d 14h	/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v
22	Release 1.2	sfielding	6461d 11h	/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v
20	Fixed RX clock recovery bug, and RX time out bug	sfielding	6692d 09h	/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v
18	Added dual clock, fixed slave bug, added reset register	sfielding	6797d 00h	/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v
14	Added LS keep alive, fixed clock recovery bug	sfielding	7045d 10h	/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v
9	Fixed bus turn-around problems, added version number	sfielding	7093d 01h	/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v
5	Removed html documentation	sfielding	7126d 00h	/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v
2	Created	sfielding	7194d 11h	/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v