URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [usbDevice/] [syn/] [xilinx/] [usbDeviceXilinxTop/] [pll_48MHz_xilinx.v] - Rev 40

Rev	Log message	Author	Age	Path
40	New directory structure.	root	5727d 17h	/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.v
37	usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project	sfielding	5925d 02h	/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.v