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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram.v] - Rev 17

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16 changed power of two style unneback 5640d 03h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
15 doc updated
gray_counter_defines added
dual port RAM updated
unneback 5643d 20h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
12 no mux on dual port mem read unneback 5701d 22h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
4 unneback 5708d 05h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
2 unneback 5708d 06h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v

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