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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram.v] - Rev 32

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Rev Log message Author Age Path
26 added ACTEL synthesis directive as define, +ACTEL unneback 5064d 06h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
18 ADDR and DATA width set to 8 resp 32 unneback 5223d 05h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
16 changed power of two style unneback 5490d 14h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
15 doc updated
gray_counter_defines added
dual port RAM updated
unneback 5494d 07h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
12 no mux on dual port mem read unneback 5552d 09h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
4 unneback 5558d 16h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
2 unneback 5558d 17h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v

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