URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram.v] - Rev 32

Rev	Log message	Author	Age	Path
26	added ACTEL synthesis directive as define, +ACTEL	unneback	5068d 07h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
18	ADDR and DATA width set to 8 resp 32	unneback	5227d 07h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
16	changed power of two style	unneback	5494d 15h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
15	doc updated gray_counter_defines added dual port RAM updated	unneback	5498d 09h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
12	no mux on dual port mem read	unneback	5556d 11h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
4		unneback	5562d 17h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
2		unneback	5562d 18h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v