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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram_dc_dw.v] - Rev 32

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Rev Log message Author Age Path
26 added ACTEL synthesis directive as define, +ACTEL unneback 5059d 17h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
18 ADDR and DATA width set to 8 resp 32 unneback 5218d 17h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
17 based on updated versatile counter unneback 5222d 15h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
15 doc updated
gray_counter_defines added
dual port RAM updated
unneback 5489d 19h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
12 no mux on dual port mem read unneback 5547d 21h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
8 unneback 5553d 20h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
7 unneback 5553d 20h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
4 unneback 5554d 03h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v

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