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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 17

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12 added wishbone comliant modules unneback 5173d 01h /versatile_library/trunk/rtl/verilog/Makefile
5 memories added unneback 5188d 17h /versatile_library/trunk/rtl/verilog/Makefile
4 added counters unneback 5192d 20h /versatile_library/trunk/rtl/verilog/Makefile
3 various updates
counter added
unneback 5195d 16h /versatile_library/trunk/rtl/verilog/Makefile

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