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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 69

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Rev Log message Author Age Path
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4982d 06h /versatile_library/trunk/rtl/verilog/Makefile
44 added target independet IO functionns unneback 5122d 05h /versatile_library/trunk/rtl/verilog/Makefile
40 new build environment with custom.v added as a result file unneback 5130d 10h /versatile_library/trunk/rtl/verilog/Makefile
33 updated wb3wb3_bridge unneback 5152d 01h /versatile_library/trunk/rtl/verilog/Makefile
29 updated counter for level1 and level2 function unneback 5179d 07h /versatile_library/trunk/rtl/verilog/Makefile
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5180d 09h /versatile_library/trunk/rtl/verilog/Makefile
25 added sync FIFO unneback 5180d 23h /versatile_library/trunk/rtl/verilog/Makefile
22 added binary counters unneback 5183d 03h /versatile_library/trunk/rtl/verilog/Makefile
18 naming convention vl_ unneback 5185d 10h /versatile_library/trunk/rtl/verilog/Makefile
12 added wishbone comliant modules unneback 5256d 10h /versatile_library/trunk/rtl/verilog/Makefile
5 memories added unneback 5272d 01h /versatile_library/trunk/rtl/verilog/Makefile
4 added counters unneback 5276d 05h /versatile_library/trunk/rtl/verilog/Makefile
3 various updates
counter added
unneback 5279d 00h /versatile_library/trunk/rtl/verilog/Makefile

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