URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 72

Rev	Log message	Author	Age	Path
60	added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed	unneback	4922d 16h	/versatile_library/trunk/rtl/verilog/Makefile
44	added target independet IO functionns	unneback	5062d 15h	/versatile_library/trunk/rtl/verilog/Makefile
40	new build environment with custom.v added as a result file	unneback	5070d 20h	/versatile_library/trunk/rtl/verilog/Makefile
33	updated wb3wb3_bridge	unneback	5092d 11h	/versatile_library/trunk/rtl/verilog/Makefile
29	updated counter for level1 and level2 function	unneback	5119d 17h	/versatile_library/trunk/rtl/verilog/Makefile
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	5120d 19h	/versatile_library/trunk/rtl/verilog/Makefile
25	added sync FIFO	unneback	5121d 09h	/versatile_library/trunk/rtl/verilog/Makefile
22	added binary counters	unneback	5123d 13h	/versatile_library/trunk/rtl/verilog/Makefile
18	naming convention vl_	unneback	5125d 20h	/versatile_library/trunk/rtl/verilog/Makefile
12	added wishbone comliant modules	unneback	5196d 20h	/versatile_library/trunk/rtl/verilog/Makefile
5	memories added	unneback	5212d 11h	/versatile_library/trunk/rtl/verilog/Makefile
4	added counters	unneback	5216d 15h	/versatile_library/trunk/rtl/verilog/Makefile
3	various updates counter added	unneback	5219d 10h	/versatile_library/trunk/rtl/verilog/Makefile