URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Rev 25

Rev	Log message	Author	Age	Path
21	reg -> wire in and or mux in logic	unneback	5103d 06h	/versatile_library/trunk/rtl/verilog/clk_and_reset.v
18	naming convention vl_	unneback	5104d 18h	/versatile_library/trunk/rtl/verilog/clk_and_reset.v
17		unneback	5168d 07h	/versatile_library/trunk/rtl/verilog/clk_and_reset.v
4	added counters	unneback	5195d 13h	/versatile_library/trunk/rtl/verilog/clk_and_reset.v
3	various updates counter added	unneback	5198d 08h	/versatile_library/trunk/rtl/verilog/clk_and_reset.v