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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Rev 29

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Rev Log message Author Age Path
21 reg -> wire in and or mux in logic unneback 5100d 14h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
18 naming convention vl_ unneback 5102d 01h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
17 unneback 5165d 14h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
4 added counters unneback 5192d 20h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
3 various updates
counter added
unneback 5195d 15h /versatile_library/trunk/rtl/verilog/clk_and_reset.v

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